1) Field of the Invention
This invention relates generally to fabrication of MOS transistors and more particularly to the fabrication of a vertical transistor by selective epitaxial growth and delta doped silicon layers.
2) Description of the Prior Art
Field effect transistors (FET""s) are a fundamental building block in the field of integrated circuits. FET""s can be classified into two basic structural types: horizontal and vertical. Horizontal, or lateral, FET""s exhibit carrier flow from source to drain in a direction parallel (e.g. horizontal) to the plane of the substrate on which they are formed. Vertical FET""s exhibit carrier flow from source to drain in a direction transverse to the plane of the substrate (e.g. vertical) on which they are formed.
While horizontal FET""s are widely used and favored in the semiconductor industry because they lend themselves easily to integration, vertical FET""s have a number of advantages over horizontal FET""s. Because channel length for vertical FET""s is not a function of the smallest feature size resolvable by state-of-the-art lithographic equipment and methods (e.g. on the order of 0.25 micrometers), vertical FET""s can be made with a shorter channel length (e.g. on the order of 0.1 micrometers) than horizontal FET""s, thus providing vertical FET""s the capability to switch faster and as well as a higher power handling capacity than horizontal FET""s. There is also the potential for greater packing density with vertical FET""s.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,780,327 (Chu et al.) that shows a process for a vertical double gage FET with vertical contacts.
U.S. Pat. No. 6,001,678 (Takahashi) shows a vertical gate TX.
U.S. Pat. No. 5,545,586 (Koh) shows a Vertical TX using epitaxial layers. However, this reference differs from the invention.
U.S. Pat. No. 5,308,782 (Mazure et al.) shows a vertical TX stack using an etching involved process.
It is an object of the present invention to provide a method for fabricating a vertical transistor by selective epitaxial growth and delta doped silicon layers.
To accomplish the above objectives, the present invention provides a method of manufacturing a vertical transistor. The invention discloses a method for a vertical transistor by selective epi dep to form the conductive source drain and channel layers. The conductive source drain and channel layers are formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.
The invention""s method of fabrication of vertical transistor comprising the following steps.
A pad layer is formed over the substrate. Next, a first insulating layer is formed over a substrate. Next, we form a transistor opening through the pad layer and the first insulating layer. We form a first conductive layer over the substrate in the transistor opening. The first conductive layer has a first conductivity type. The first conductive layer is preferably formed by an epitaxial process. We form a first dielectric layer over portions of the first conductive layer and over the first insulating layer. We form a second conductive layer over the exposed portions of the first conductive layer. We form a second dielectric layer over portions of the second conductive layer and over the first insulating layer. Next, we form a third conductive layer over the exposed portions of the second conductive layer. The third conductive layer has a first conductivity type. We form a third dielectric layer over the second dielectric layer and the third conductive layer. A trench is formed through the third conductive layer the third, second and first conductive layers to at least expose the substrate. The first, second and third dielectric layers are shown as a merged dielectric layer. We next form a gate dielectric layer on the sidewalls and bottom of the trench. The gate dielectric layer is preferably comprised of silicon oxide. Then we form a gate over the gate dielectric layer and filling the trench. We form a cap dielectric layer over the merged dielectric layer. Contacts are formed through the first second and third dielectric layers (shown as layer) to contact the first, second and third conductive layers.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.